Physical Design Engineers - 2 openings

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency - unlocking unprecedented efficiency for AI training and inference at scale. Kandou's architecture is not just an incremental improvement - it's a foundational shift in how AI hardware is built for the future. We are actively seeking Physical Design Engineers based in Hyderabad OR Bangalore Required competences - Experience - 10+ years' experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role - Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm - Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc. - Expertise in Timing Constraints and Static Timing Analysis (STA) - Experience in CPF/UPF technologies and flows is highly desirable - Exposure to flip-chip package technologies and wire bond package technologies - Experience in hierarchical floor planning and im